The present invention generally relates to semiconductor memory devices and data processor devices.
A conventional example of a flash memory is described in the publication IEICE Transactions, vol. E74, pp. 130-141, 1991, written by T. Masuhara et al. This flash memory cell has the source, drain and channel region formed on a silicon substrate surface, and the floating gate and control gate of polycrystalline silicon provided within an insulator. The memory function is achieved by effecting charge accumulation within the floating gate and by use of the change in conductance between the source and drain resulting from the increase or decrease of the amount of accumulated charges. Additionally, examples of a conventional single-electron memory using polycrystalline silicon are described in IEEE International Electron Circuit Conference, pp. 541-544, 1993, written by K. Yano et al, and in International Solid-State Circuits Conference, pp. 266-267, 1996, written by K. Yano et al. This technology is such that the channel, as a current path, and the electron capturing memory region are simultaneously formed by thin film of polysilicon. Storing of information can be performed by using the fact that the conductance of the current path is changed when an electron is captured by the memory region. In addition, the number of accumulated electrons can be controlled with high precision up to a single unit by accumulating electrons in minute memory regions, and the accumulated electrons can be stably held even at room temperature. This single-electron memory can be found, from its principle, to be suited for its extreme size reduction. Particularly, by using an elemental structure having the source and drain regions provided on an insulator film, it is possible to reduce the conductance between the current path and the surroundings and thus read out information easily from a small amount of accumulated charges. Moreover, a SRAM (Static Random Access Memory) cell, as described in IEICE Transactions, vol. E74, pp. 130-141, 1991, written by T. Masuhara et al, is an example of a memory cell having a combination of FET (Field Effect Transistor) of polycrystalline silicon and MOS (Metal-Oxide-Semiconductor) transistor provided on the substrate surface. In such a SRAM a unit memory cell contains one set of six transistors and uses a polycrystalline silicon FET for each of the two load transistors. Since the polycrystalline silicon FET can be formed on other transistors, the memory cell can be built in a smaller plan view area than when six transistors are formed on the substrate surface.
Also, an EPROM (Electrically Programmable Read-Only Memory) formed of polycrystalline silicon and described in JP-A-05-082787 is a known example of a nonvolatile semiconductor memory having a channel on an insulator.
The semiconductor memory device that stores information by accumulating charges in storage regions within an insulator and using the change of conductance between the source and drain, resulting from an increase or decrease of the accumulated charges, as represented by flash memory, contains memory cells each formed of one transistor, and thus it is suited for high-density integration. The flash memory has the merit of high-density integration and nonvolatile property, but it is three digits or more slower to rewrite than that of a DRAM (dynamic Random Access Memory). Therefore, as in digital cameras, data is once stored in a volatile memory buffer, and then is gradually transferred to a nonvolatile element. Thus, since this technique needs to provide a buffer memory as a separate chip and use a complicated control system, the cost is greatly increased as compared with the case in which only a flash memory could be used. A register is provided for each data line on the flash memory chip. One can consider dividing the data line and increase the number of registers, thereby raising the rewriting speed. However, since the register occupies a large area, the chip area would be increased, and thus the cost would still rise.
In addition, if the capacitance of a data line is reduced simply from the view point of improving the performance of semiconductor memory devices, the time necessary for charging and discharging is thereby shortened at the time of writing, erasing or reading. Thus, such a device is suited for high-speed operation, and can operate with low consumption of power because a small amount of charges are to be charged or discharged. This is, also, true for word lines. On the other hand, the memory cell array region must still expand in its area to achieve a great increase of memory capacity even though the very small size memory cell capability is taken into consideration. Therefore, the data lines and word lines, which run between the ends of the array, would become long thus increasing their capacitance. A counter-measure for solving this problem can be to divide the cell array into smaller units, and perform a write or read for this unit. However, if peripheral circuits such as a sense amplifier and word line driving circuit are provided for each such small unit, an increase of the memory area will occur as a new problem.
Moreover, in terms of cost reduction and improvement in speed of data transfer between memory and processor, the DRAM and flash memory should be designed to be on a single chip in a practicable way. However, because the memory cell production process and the logic-purpose CMOS production process are not matched well with each other, it is thereby difficult to combine both the memory performance and the logic performance.